Interconnection networks for multi-processor systems, high-end routers, switches, and other devices are designed and implemented using many different approaches. The interconnection network can be a critical factor in determining the performance of a multiprocessor system. In particular, the latency and bandwidth of the network can affect system properties, such as the performance of the system during remote memory accesses.
Interconnection network routers are constrained by the “off-chip” bandwidth that can be effectively coupled to an integrated circuit (IC) used for routing control. The amount of such off-chip bandwidth has steadily increased due to advances in signal technology. The bandwidth of an IC is a factor of both the number of ports on the chip and the bandwidth of each port on the chip. Thus, in order to realize an increase in bandwidth, the IC's bandwidth per port or the number of ports (or both) must be increased. Many applications have increased the total bandwidth by increasing the bandwidth per port; however, in certain instances it is desirable to increase the total bandwidth by increasing the number of ports. Commonly used interconnection router architectures exhibit problems with both throughput and with the complexity of various components of the interconnection device as the number of ports increases. Additionally, the physical size limitations of the routers and switches for multi-processor systems are more restrictive than the limitations for routers and switches for other applications, such as the routing of Internet Protocol (IP) packets.
These and other characteristics present challenges to the implementation of interconnection network routers.